rules_vivado

Bazel rules for Xilinx Vivado FPGA synthesis, placement, routing, and bitstream generation. HDL sources flow in through rules_verilog (VerilogInfo) and rules_vhdl (VhdlInfo); the same *_library targets are reused for simulation and synthesis.

The public surface is:

• vivado_toolchain — wraps a shell script that sources your Vivado install. Mandatory: every vivado_* rule resolves it through Bazel toolchain resolution.
• Per-phase rules — vivado_synthesize, vivado_placement / vivado_routing, vivado_write_bitstream, plus vivado_create_project, IP packaging, and xsim_test.
• vivado_flow — convenience macro chaining synthesis → opt → placement → place-opt → routing → bitstream.

Quick start, toolchain authoring, multi-version constraint gating, and the full per-rule reference are hosted at https://hw-bzl.github.io/rules_vivado/.

License

Apache License 2.0